Engineering Academy

Engineering Academy Tackles RISC-V in Next Educational Event Installment

Aug. 23, 2022
The Sept. 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software and a robust panel discussion.

The open-source RISC-V instruction set architecture (ISA) has taken the development community by storm as more companies have implemented chips based on RISC-V. The architecture is empowering a generation of developers by giving everyone, regardless of size, an opportunity to compete. It’s also fostered a level of customization that’s driving innovations in areas from microcontrollers to artificial intelligence.    

As part of the new Engineering Academy educational platform, a Sept. 8 event on Expanding the RISC-V Ecosystem from our colleagues at Electronic Design will delve into RISC-V from multiple perspectives. Each session, led by industry leaders and subject matter experts, will cover topics ranging from chip and architecture designs through software development.  

The incredible panel of experts will discuss how the open-source RISC-V architecture will enable chip design, and how it can promote industry-wide collaboration to build solutions based on a common set of standards and specifications. Panelists include:

  • Calista Redmond, CEO, RISC-V International
  • Dirk Akemann, head of marketing, SEGGER
  • Drew Barbier, senior director of Product Management, SiFive
  • Rupert Baines, CMO, Codasip

Technical sessions will include:

RISC-V Architecture Considerations

The adoption of RISC-V and the expansion of accessible markets is directly related to the extent the design ecosystem and infrastructure has been developed. We talk to Jeff Hancock at Siemens Embedded about how the development for that ecosystem is progressing.

RISC-V from the Chip Perspective

RISC-V is promising lots of things, but you still have to be able to build a chip with it. In this tech session, we talk about the RISC-V ecosystem from the point of view of IP cores and ISAs. Drew Barbier Sr., director of Product Management from SiFive, will shed light on this topic.

Reference Models for RISC-V Processor Verification and Software Development

The open standard ISA of RISC-V gives new degrees of design freedom to system designers, software developers and processor hardware implementers. Supporting the ISA specification is the growing ecosystem of partners who provide the essential infrastructure that developers can rely on from project inception to production. Simon Davidmann from Imperas will cover adaptable verification methods that complement the design innovations of RISC-V, plus the use of virtual platforms for software development and architectural exploration with RISC-V custom instructions.

Registration is free, and prizes can be won by active session visitors who aggregate the most points.

About the Author

William G. Wong

Bill Wong is senior content director for Electronic Design.

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