Allison Carter, Georgia Tech

Low-Power Chip Lets Robots Learn and Collaborate

April 10, 2019
This chip uses a hybrid digital-analog time-domain processor that encodes information in signals’ pulse widths.

Researchers at the Georgia Institute of Technology have developed an ultra-low-power neural-network chip inspired by the brain that could let palm-sized robots collaborate and learn from their experiences. Combined with new generations of low-power motors and sensors, the new application-specific integrated circuit (ASIC), which operates on milliwatts of power, could help intelligent swarm robots operate for hours instead of minutes.

“We are trying to bring intelligence to small robots so they can learn about their environment and move around autonomously,” says Georgia Tech professor Arijit Raychowdhury. “To do that, we want to let low-power circuits in small robots make decisions on their own. There is a huge demand for small, but capable robots.”

To conserve power, the chip uses a hybrid digital-analog time-domain processor in which signals’ pulse-width encodes information. The neural network IC accommodates model-based programming and collaborative reinforcement learning, potentially giving small robots larger capabilities for reconnaissance, search-and-rescue, and other missions.

A robotic car controlled by an ultra-low power hybrid chip. (Photo: Allison Carter, Georgia Tech)

In time domain computing, information is carried on two different voltages encoded in the width of the pulses. That gives the circuits the energy-efficiency advantages of analog circuits with the accuracy and durability of digital devices.

“The size of the chip is reduced by half, and power consumption is one-third what traditional digital chips need,” Raychowdhury explains. “We used several techniques in logic and memory design that cut power consumption to the milliwatt range while still meeting performance targets.”

With each pulse-width representing a different value, the system is slower than digital or analog devices, but Raychowdhury says the speed is sufficient for the small robots. “For these control systems, we don’t need circuits that operate at several gigahertz because the devices don’t move that quickly,” he notes. “We sacrifice a little performance to get extreme power efficiencies. Even if the chip operates at 10 or 100 megahertz, that will be enough for our applications.”

Georgia Tech researchers have developed an ultra-low power hybrid chip inspired by the brain that could help give palm-sized robots the ability to collaborate and learn from their experiences. (Photo: Allison Carter, Georgia Tech)

The 65-nanometer CMOS chips accommodate both kinds of learning appropriate for a robot. It can be programmed to follow model-based algorithms or learn from its environment using a reinforcement algorithm encourages better performance over time. It’s much like a child who learns to walk by bumping into things.

“You start the chip with a predetermined set of weights in the neural network so the robot it controls starts from a good place and not crash immediately or give erroneous information,” Raychowdhury explains. “When you put it in a new location, the environment will have some structures the chip will recognize and some it will have to learn. It then make decisions and will gauges the effectiveness of each decision to improve its ability to move.”

Communication between the robots let them collaborate to seek a target. “In a collaborative environment, the robot not only needs to understand what it is doing, but also what others in the same group are doing,” Raychowdhury says. “They work to maximize the total reward of the group as opposed to the reward of the individual.”

A Georgia Tech researcher places a robotic car controlled into a test arena where it will learn and collaborate with another robot. (Photo: Allison Carter, Georgia Tech)

Model cars built by the researchers use the new ASIC to take information from inertial and ultrasound sensors to determine their location and detect objects around them. The ASIC is also continuously communicating with chips in other cars. The goal for the chip is to steer the car to find a target while avoiding traffic cones and other cars.

Three major subsystems consume power in each car: the motors and controllers used to drive and steer the wheels, the processor, and the sensors. Because the ASIC uses little power, the motors consume the bulk of the power. “We have been able to push the computing power down to a level where the budget is dominated by the needs of the motors,” he says.

The team is now developing micro-electromechanical (MEMS) motors that operate with much less power than conventional motors. They are also trying to combine the computation and control circuitry on a single chip.

“We want to build a car in which sensors, communications, computers, and actuation are at about the same power level, on the order of hundreds of milliwatts,” says Raychowdhury. “If we do, the cars should run of several hours on two AA batteries. We now have an idea what kind of computing platforms we need, but we still need the other components to catch up.”

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