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The bad news for makers of semiconductor- manufacturing equipment is that sales of most kinds of fab gear are flat to down. The good news is that the U.S. could end up playing a bigger role supplying manufacturing equipment for the emerging area of solid-state lighting.
“The U. S. Dept. of Energy used stimulus funds to amplify the supply-chain strengths of the U.S. The DOE recognized that the U.S. would be an unlikely place for LED fabs, so it tried to seed the development of LED-manufacturing equipment here,” explains Tom Morrow, executive vice president, emerging markets group and chief marketing officer for SEMI, the association serving the manufacturing supply chain for electronics makers. “Going forward, it looks as though assembly and automation areas, rather than front-end LED fabs, will be a likely focus for the U.S.”
LED-manufacturing equipment will be among the focus areas when the upcoming Semicon West show kicks off in San Francisco July 10. Though LED-manufacturing equipment is a promising area, it saw a modest drop in sales last year. “The display market was the big engine for LEDs, but it has declined partly because TV sales have cooled off, but also because set makers are backlighting more efficiently. Two years ago, a 40-in. TV might contain 240 LEDs for backlighting. Now some TVs only use 20 or 30 because the LEDs are brighter, and manufacturers have learned how to distribute the lumens more efficiently,” says Morrow.
Virtually all the recent investment in LED-manufacturing equipment has been for high-brightness LEDs, says Morrow. Much of this spending has been on MOCVD (metalorganic vapor phase epitaxy) equipment, which has led to overcapacity, particularly in China. Though solid-state lighting was the original application envisioned for the LEDs coming off these machines, some fabs have now switched over to making LEDs for mid and low-power uses, Morrow says.
Makers of high-brightness LEDs have several technical challenges to overcome. One is a transition from 4 to 6-in. (100 to 150 mm) wafers. LED makers are also trying to move away from sapphire substrates — used because they are compatible with GaN material that goes into LEDs — and toward silicon substrates, which are less expensive but can have problematic interactions with GaN.
Overall, SEMI expects sales of semiconductor- manufacturing equipment to decline about 10% this year after a boom in 2011. However, recent announcements about capital-equipment purchases from big chipmakers such as Intel, Santa Clara, Calif., suggest that 2012 could merely turn into a flat year, Morrow says. Booming sales of tablets, smartphones, and other mobile platforms, as well as the growing ranks of wealthier consumers in emerging markets such as China and India, are driving the demand for consumer electronics and ICs that power them.
Semicon West will also host discussions of several technological issues that equipment makers must overcome to continue along the road toward higher chip densities that Moore’s Law predicts. “For the first time in the industry’s history, there are several challenges coming together at the same time,” says Morrow. One of these is extreme ultraviolet lithography (also known as EUV or EUVL), a next-generation lithography technology using extreme ultraviolet wavelengths on the order of 13.5 nm. EUVL is considered a “must” for making chips having features on the order of 11 nm, but it is significantly more complicated than the deep ultraviolet lithography used to make ICs today. For one thing, EUV lithography must take place in a vacuum. Because EUV technology requires high vacuum, the transfer of wafers into and out of the tool chamber is cumbersome and limits the speed at which wafers can be processed.
Moreover, the optics typically absorb over 95% of the available EUV light, so the EUV source must be superbright. And there are other difficulties associated with shadowing, diffraction patterns, and imperfections that degrade patterns put on chips.
Another issue facing chip manufacturers this year is the transition to 450-mm wafers from 300-mm versions. Wafers this large need handling equipment and metrology that is completely different than that for managing smaller wafers. What’s worse, it’s likely the first 450-mm facilities will also have to implement EUV lithography. This puts chip fabs in the position of having to iron out bugs in two new technologies simultaneously.
Finally, chipmakers are also transitioning away from planar transistors toward those that employ more of a 3D structure. This helps reduce leakage current during the off state of the device, a problem that becomes more severe with ever-smaller dimensions characterizing chip circuitry today. The typical approach is to locate several gates on multiple stacked surfaces, which more effectively suppresses “off-state” leakage current. The result is lower power consumption and a more-compact layout than on conventional planar transistors.
The difficulty with 3D designs is that they will only become practical with significant advances in semiconductor- manufacturing-process technology, says Morrow. For example, Intel has been working on its 3D transistor technology, which it calls a trigate architecture, since 2002. But the company only ironed out associated massproduction issues last year. Intel factories are expected to make upgrades this year so they can manufacture the company’s Ivy Bridge CPUs which will be built with trigate transistors.