But a technique that puts liquid-cooling channels onto the backs of ICs could significantly boost cooling rates and make 3D chips more practical, say developers at the Georgia Institute of Technology
Some existing liquid-cooling technology uses high-temperature bonding to attach separate cooling modules or build microchannels onto chip backs. But modules have limited heat-transfer rates, and bonding temperatures of 400 to 700°C can damage circuits. In contrast, Georgia Tech's CMOS-compatible technique works at temperatures <260°C and builds microfluidiccooling channels without damaging attached circuits. The scheme works on gigascale integrated (GSI) chips and is fully compatible with conventional flip-chip packaging.
Researchers begin by etching trenches about 100- m deep on back of a silicon wafer. A sacrificial layer of high-viscosity polymer fills in the trenches. Next, a polishing step removes excess polymer. A porous overcoat covers the filled trenches and the chip is gradually heated in a nitrogen atmosphere. The heating decomposes the sacrificial-polymer, leaving behind the microfluidic channels. The porous overcoat is then covered with another polymer layer to make a watertight system. Buffered, deionized water acts as a coolant.
Self-contained systems would employ tiny micropumps to circulate coolant, while more complex equipment could use a centralized circulation system. Microchannels have been shown to withstand pressures exceeding 35 psi and should be capable of cooling rates of 100 W/cm2. Cooling capacity depends on coolant flow rate, pressure, and channel size. Smaller diameter microchannels more efficiently transfer heat than larger ones. Researchers have also built through-chip holes and polymer pipes that would connect an on-chip cooling system to channels embedded in a printed-circuit board.
The technology will probably first find use in high-performance specialty processors. So far, the tiny cooling systems have run for several hours without failure, though additional testing is still needed. Funding for the research comes from the Microelectronics Advanced Research Corp. and Darpa.
