Machine Design

Nanotube transistors fit for space

U.S. Navy Research Lab

Researchers at the U. S. Navy Research Laboratory in Washington, D.C., are designing single-walled carbon nanotube-based transistors (SWCNT) that are protected against the ionizing radiation found in outer space and the Van Allen Belt, a ring of charged particles circling Earth. This radiation can degrade ICs, interfere with their proper operation, and lead to premature failures.

Radiation affecting ICs takes two forms. In one, an ionizing particle makes a direct hit on the transistor, which can corrupt data and signals. But the chances of such a hit on a SWCNT is small due to their tiny size, low density, and inherent isolation from other SWCNTs in a device, according to Navy scientists. The other form results from the cumulative effect of charges trapped in electronic devices’ oxides, including the gate oxide and those that isolate adjacent devices. These trapped charges shift the voltage needed to turn the transistor on or off, which leads to power leaks and eventual failure of the entire circuit.

To prevent charges from accumulating, researchers built a SWCNT with a thin gate oxide layer made of silicon oxynitride. This hardened dielectric material keeps out stray charged particles.

Making SWCNT “spaceproof” means future circuitry on spacecraft will have less redundancy and error-correction circuity than today’s spacebound ICs and electronic equipment. This would reduce costs and power consumption while improving performance, even if SWCNTs operate at the same speed as present day circuits.


© 2012 Penton Media, Inc.

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