PC systems Pony up to PCI Express

March 20, 2003
A speedy new format for computer I/O will start showing up on systems later this year.

Leland Teschler
Executive Editor

Developers say PCI Express will make it possible to devise computer systems configured differently than those of today. One proposed concept is to separate the main CPU tower from the rest of the system. A PCI Express connection would provide enough bandwidth to link the tower to the operator interface and removable media. For mobile and embedded systems, developers see mini PCI Express plugs eliminating edge connectors used on mezzanine and other add-in boards. Resulting platforms may be smaller than those of today.

Tyco Electronics Corp. connectors for x1, x4, x8, and x16 lanes (The spec reserves x2 lane configurations for cable connections rather than circuit boards). One concept for evolving to the PCI Express format is to devise plug-in boards with both ordinary PCI and Express connections. Plug-in boards could take advantage of Express on CPU boards that provide it; otherwise they would revert back to operation over PCI. Express's backward compatibility with PCI protocols makes this option possible.

PCI Express connections consist of one or more lanes, with each lane containing two pairs of wires. Each pair runs between the transmitter and receiver of two communicating devices. Signals are differential rather than referenced to ground, reducing problems with electrical noise. Data sent over a PCI Express link incorporates a clock signal (mixed into the data via 8b/10b encoding) and gets divided up depending on how many lanes are in the link. For example, a one-lane link sends all data in the order it was issued. Systems with multilane links portion out data packets in round robin fashion among the links in the system. Moreover, two systems with a mismatched number of PCI Express lanes can still talk to each other. Express circuits are smart enough to sense the number of lanes available and handle data packets accordingly.

Computer architects suggest that future systems will increasingly take a form that incorporates the building blocks portrayed here. Note that an I/O bridge circuit, rather than a multidrop bus, handles input/output tasks from most devices. Most PCI Express devices would connect to the I/O bridge through a switch. Graphic subsystems would connect by PCI Express directly to a memory controller. As a transition for older peripherals, systems will probably also incorporate conventional PCI bus connections from their I/O bridge.

If you've ever plugged a peripheral board into a modern PC system, there's a good chance it had a PCI interface. Developed in the early 1990s, PCI (for Peripheral Component Interconnect) has become a pervasive I/O backplane. It's found not only in desktop computers, but also in servers and communication devices. Even embedded systems use a version of it called Compact PCI.

Increasingly, however, PCI has run out of steam for handling ever-higher bandwidths and data-intensive computer operations. The demands of new computer platforms exceed what the PCI bus can provide. Both Gigabit Ethernet and 1394b networking, for example, need bandwidth that exceeds PCI's 133 Mbits/sec shared maximum.

Enter PCI's successor. Called PCI Express, it will handle data-transfer bandwidths to 25 Gbits/sec/lane/direction initially. Future versions will run even faster.

It looks as though the first board and system-level products incorporating the spec will emerge later this year. "Typically it's 12 to 18 months from the time you release a spec to the point when products appear," says Intel Program Manager for PCI technologies Ramin Neshati. "We're expecting our initial silicon building blocks late this year. That will trigger the volume-ramp-up of products." Neshati expects the first applications to be in graphics, followed quickly by networking products. He also thinks there will be a place for PCI Express on servers, where it can reduce the complexity of motherboards and I/O connections.

One interesting aspect of PCI Express is that it's more than a faster format for plug-in cards. One version of the spec, for example, lets computer components talk to each other over a cable several feet long. This will let system designers physically separate components, if need be, into different enclosures. One potential result: No more kicking the CPU tower under your desk. "With these disaggregated systems," says PCI Special Interest Group chair Tony Pierce, "you could build high-power components into a separate enclosure that could sit in a closet somewhere. The box on the desktop could be smaller, maybe just containing the graphics and USB controller. In other words, just the I/O expansion would be on the desktop."

The PCI SIG is in the initial phases of evaluating the cabled version of PCI Express. Topics such as the maximum length of the cable are still under discussion. But Pierce thinks such issues will be decided soon and that commercial products using it could debut next year. "You may even see initial products from inventive OEMs before the spec is final," he says. "Nothing in the spec says you can't do that."

Of course, the transition from PCI to PCI Express won't be immediate. The first desktop systems to carry PCI Express sockets will almost certainly also include connections for ordinary PCI as well. And the PCI SIG is now defining a PCI-to-PCI Express bridge that will let older boards work with the new format. All in all, ordinary PCI slots are likely to be found in mid to low-end desktop systems for some time to come.

Speed on board

A review of trends in electronics makes it clear why PCI is running out of gas. PCI, like most backplane buses, uses parallel signals that are issued in sync with a clock signal. As clock frequencies rise into the gigahertz range, it becomes more and more problematic to devise circuit boards able to support parallel connections. One reason is that all signal traces on the board that connect to the parallel bus must have nearly identical lengths. Otherwise some signals would be too late arriving at the bus connections, leading to bad data. Power and ground noise both get progressively worse as frequencies rise to the gigahertz range, as do skin effects and dielectric losses. These tend to affect signal rise and settling times, a problem because PCI specifies logic levels in terms of signal rising edges.

In contrast to the old PCI, PCI Express is based on serial differential links rather than a parallel bus. Zero crossings of differential signals, rather than rising edges, are used to denote logic levels. The differential signal is derived from the voltage difference between two conductors. This scheme works well with the sub 5-V logic levels found on today's circuitry.

Another key facet of PCI Express is that is can be deployed in multiple widths, unlike old parallel bus schemes that had one fixed set of signals. The reason is that PCI Express is a serial architecture. Data bytes get transmitted sequentially over one or more four-wire lanes. A given PCI Express connection can hold up to 32 separate lanes of four wires each. Thus PCI Express actually consists of multiple independent serial connections grouped together.

The four wires in each lane are in two-wire pairs. One pair goes from the transmitter on one device to the receiver on another. The other pair handles the reverse path. A point to note is that only two devices are on the connection. There is no multidrop sharing of bus lines as in older plug-in board connections. In PCI Express, a switching IC replaces the multidrop bus. This switch fans out signals for the PCI Express I/O. It can be a separate logic element or integrated into some other IC.

In this regard, PCI Express can serve as more than just a means of handling plug-in boards. Its serial protocols are sufficiently general purpose for chip-to-chip use as well as for attaching other interconnects like 1394B, USB 2.0, Ethernet, and next-generation graphics.

Use of a serial architecture simplifies the task of scaling up the speed of data transfers. One reason is that each lane has its own clock signal superimposed on the signaling wires. This eliminates the need to synchronize numerous connections to one clock, as is necessary on parallel buses. It also eliminates the problem of synchronization among numerous far-flung connections, which becomes difficult on a parallel bus as clock frequencies rise into the gigahertz range.

The clock frequency spelled out for the first generation of PCI Express yields a data rate of 2.5 Gbytes/sec/direction. Developers expect advances in IC technology to eventually push the rate to 10 Gbytes/sec/direction, considered the practical maximum for signals in copper circuit-board traces. And it looks as though PCI Express could still be in use even when printed-circuit boards give way to something faster. "We don't know at what clock frequency PCI Express runs out of steam," says Intel's Ramin Neshati. "We haven't yet found the speed at which it breaks compliance."

Operating system views

Intel says all operating systems will be able to boot without modification on a PCI Express platform. That's because the new spec uses the same configuration scheme as ordinary PCI.

"The spec was designed so that any operating system that was PCI 2.2-compliant should boot and run without modification," says PCI SIG's Tony Pierce. "It would just think there were some very fast PCI devices on the system. That said, there are some features of PCI Express you won't get in that situation. For example, you wouldn't see advanced error reporting and some of the more aggressive active-state power-management functions until you have an operating system that natively supports PCI Express."

Use of layered protocols eases the transition from old PCI to the new spec. For years, standards committees have defined communication protocols in self-contained layers. The idea is to isolate code written for one part of the protocol from that of others. This allows upgrading one of the three layers defined for PCI Express (transaction, data link, and physical) without forcing a change to the others.

Charging up with PCI Express cards

PCI Express board connectors will have widths of x1, x4, x8, and x16. Legacy PCI slots will probably sit next to native PCI Express connectors on most CPU boards initially. The serial nature of the PCI Express protocol will make it possible to plug smaller PCI Express cards into larger slots -- PCI Express circuits will be smart enough to discern that fewer lanes are connected, then configure themselves to handle what they find.

Mobile cards devised for laptops and similar portable devices will need special right-angle edge card connectors. Cable connectors, too, will be available eventually for the spec. Among the first to supply connectors for PCI Express is Tyco Electronic Corp., Harrisburg, Pa. (www.tycoelectronics.com). Tyco Business Development Manager Bob Atkinson says the first companies to sample Tyco's PCI Express connectors are desktop computer makers, some of whom, he thinks, may begin using the connectors in high volume by the end of this year. But most computer makers will wait until mid 2004 to begin shipping in earnest.

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