Top technical challenges in semiconductor manufacturing

July 7, 2005
Immersion lithography, low-k materials, and metrology are on the list.

Chip lithography and front-end fab processes weigh heavily in current research efforts, but also important is the conservation of energy consumption in manufacturing tools, and the growth of environmental regulations. So says Sematech, the technology development consortium that promotes interests of chipmakers.

Sematech issues a top challenges list as a guide for directing its resources on the most critical of about 75 projects it maintains in key areas of chip R&D. The consortium develops the list through its executive steering council in consultation with corporate managers.

In the area of lithography, Sematech's focus is on resolving the few remaining manufacturability issues associated with immersion lithography. This technique has been developed as a method for extending the resolution and depth-of-focus of optical lithography. It does so by interposing a liquid between the exposure tool's projection lens and a wafer.

Prototype immersion tools are beginning to arrive in advanced manufacturing labs. Sematech technologists are particularly interested in areas such as coating durability. An additional program will determine how extensible the techniques are to 45-nm half-pitch features and beyond.

Sematech is also looking at mask infrastructure as a means of improving the capabilities and reducing the overall cost of photomasks for both 193-nm immersion and extreme ultraviolet (EUV) lithography.

Similarly, Sematech is trying to determine the practical and theoretical limits of chemically amplified resist platforms. The consortium is supporting work on new materials and approaches for 193-nm immersion, and emphasizing ultimate resolution, line edge roughness (LER) and sensitivity for EUV resists.

EUV infrastructure includes the development of critical technology components to let extreme ultraviolet lithography become practical for manufacturing later in the decade. Sematech says it will focus on developing systems for defect and free mask blanks, EUV sources, and mask handling and photoresists. It also wants to devise ways of assessing optics lifetimes.

In front-end processes, Sematech is looking at advanced gate stack technology, involving development of high-k dielectrics for logic and memory products, metal-gate electrodes, dual workfunction metal-gate-transistor processes, and various electrical characterization methods for metal/high-k devices. The advanced gate stack (AGS) program focuses on delivering reliable gate stack technology for the 45-nm node and beyond.

Also of interest is nonclassic CMOS, an approach to the challenges posed by ever smaller scaling of chip features. Non-classical CMOS includes infrastructure development for alternative device technologies such as strained silicon, silicon-on-insulator (SOI), double-gate metal-oxide semiconductor field-effect transistors, and multigate FETs (MuGFETs). Similarly, programs focused on planar bulk transistor scaling will try to develop technologies to enable the continuation of conventional Mosfet scaling for as long as possible. Potential solutions include channel material engineering (GeOI, III-V channel, hybrid silicon); advanced strain engineering; new doping and annealing approaches; and metallic junctions.

In interconnect technology, Sematech is looking at low-k dielectrics and process compatibility. Low-k is critical to advanced semiconductor manufacturing because it reduces line-to-line capacitive coupling and lets metal lines pack more closely on the chip, with less risk of electrical signal leakage.

After identifying and screening a number of new low-k materials, Sematech engineers are evaluating two low-k candidates in two-level metal integration work. Additionally, Sematech technologists will try to understand and address the resistivity rise in narrow copper lines, and the development of advance barrier and fill solutions.

Metrology is on the list because it is a critical enabler for more densely packed chip features. Metrologists at Sematech will evaluate commercially available metrology tools for critical dimension scanning electron microscopy (CD-SEM), optical critical dimension (OCD) and overlay, and commercial defect inspection and redetection tools, for the 45-nm technology node and beyond. The idea is to free Sematech company members from having to do the required benchmarking on their own.

Finally, the consortium is undertaking a series of factory and equipmentrelated projects aimed at improving both equipment and overall factory productivity, and reducing costs in fabs. These projects include emanufacturing, advanced equipment and process control, advanced equipment software testing, short cycle time and short ramp-ups, equipment and fab agility, and development of standards.


Sematech Inc.

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