Machine Design

Honey, I shrunk the circuit board

As electronic components and products continue to shrink in size, circuit miniaturization techniques keep pace.

Stud bumps provide a contact system with the conductive properties of solder that is compatible with glued flip-chip processes.

Modern products provide less and less space for flat, rigid circuit boards. This trend is forcing designers to innovate and come up with substrates that don't fit the definition of the conventional circuit board. A recent example of this trend is a technique called 3D CSP (chip-scale processing). 3D CSP builds on older miniaturization techniques by folding the circuit substrate to save space.

Miniaturization in brief
Electronic-circuit-miniaturization techniques have evolved over the years. One of the earliest methods was the Chip On Board (COB) technique. At the core of COB is the use of integrated circuits (ICs) in unpackaged form. After being sawed from completed IC wafers, the unpackaged integrated circuits are glued to a circuit-board substrate with the contact pads facing away from the substrate. IC pads are connected to the substrate with fine-bonded wires, and various types of surface-mount devices are wave-soldered to the substrate to complete the circuit. The IC is then encapsulated for structural rigidity and environmental protection. Eliminating plastic or ceramic packaging and solderable leads associated with finished ICs saves up to 50% of the surface area required by conventional circuit layouts.

The flip-chip process is a successor to COB. The flip-chip technique eliminates the surface area around the IC used for wire bonding. As with COB, flip chip is compatible with flexible circuit boards. Unlike COB, however, the raw IC mounts with the contact pads against the circuit board, where they align with contact pads on the substrate. This eliminates bonded wires so other flip chips or reflow-soldered components can be placed within a millimeter of each other.

There are several different versions of flip chip differentiated by how the chip attaches to the circuit board: gold-to-gold stud bumping, reflow soldering, and isotropic conductive adhesive.

Gold-to-gold stud bumping uses nonconductive adhesives in conjunction with metallic stud bumps deposited on IC chip pads prior to attachment. A machine deposits gold stud bumps with varying heights, diameters, and shapes on the IC pads then aligns them with adhesive on the PC board, pushing them together and heat-curing the joint. The parts wipe against each other, making contact. The only bond between the PC board and the die is the adhesive itself. The adhesive, a proprietary mixture, is designed to minimize water absorption and have fast curing times to increase throughput.

The bond is not a eutectic joint as with a solder connection. With a solder joint, any movement can crack the joint. Temperature is also an issue. Normally, stable temperatures don't pose a problem. But with changes in temperature, shapes will change at different rates causing solder joints to break into many small cracks called microcracks.

This method is practical for small to medium production runs, up to 1 million units. It's more cost effective at these quantities than other flip-chip processes because it doesn't require any special preparation of IC chips other than bumping, and it provides electrical performance equal to that of soldered connections.

When production gets above a million units, reflow soldering wins out. Reliability and cost are the biggest factors. The trade-off with stud bumping is the need to place a bump on each pad, which increases preparation time. In reflow soldering, a screen is placed over the wafer with cutouts over the pads and solder is poured on top. This saves time and increases throughput.

Lastly, conductive adhesives contain small conductive balls. When pushed together, the balls provide good conduction between the die and the PC board pads. This method works in low-current applications. It's also fairly inexpensive and doesn't require any special wafer preparation.

What's next?
Valtronic's 3D CSP technique is the highest level of miniaturization available in the industry. With 3D CSP, IC chips mount using the gold-to-gold stud bump method. The chips mount to a flexible circuit board, which is then manually rolled or folded and encapsulated to form a compact circuit module. 3D CSP packaging saves as much as 80% of the space occupied by conventionally assembled circuits, while providing even greater power efficiency than COB.

Medical electronics, such as in-the-ear hearing aids, use 3D CSP. These devices measure less than 4 mm on a side and contain multiple ICs and some 18 to 20 other electronic devices.

Three-dimensional viewing systems might also benefit from 3D CSP assembly. Until recently, such systems were a curiosity limited chiefly to applications in toys and entertainment, conjuring up images of a bulky head-mounted display associated with virtual-reality systems. But that's changing as 3D viewing systems are adopted by industry and research for visualizing complex spatial relationships in mechanical designs, molecular phenomena, and related applications.

One company wants the next generation of its LC (liquid-crystal) shuttered eyewear to be no bigger than an ordinary pair of reading glasses. Current products are slightly larger than a typical pair of wraparound industrial safety goggles, weighing just a few ounces.

However, one design factor limiting the growth and application of 3D viewing systems is form factor. A typical pair of eyeglass frames offers little in the way of cavities or flat areas to mount electronic circuits. The requirements for a power source, on-off switch, and other controls further complicate the mechanical design as well as ergonomic considerations.

The wafer-thin form factor of raw IC chips works well in the gogglelike frames of current 3D eyewear, although the gentle curves of the frames present other challenges to circuit-board design. Newer generations of 3D eyewear need flexible circuit boards to follow frame contours and provide surface area and terminals for batteries, a power switch, and other I/O connections.

In general, miniaturization improves power efficiency and operating speed of circuits by significantly reducing the resistive and reactive effects of traditional wiring and IC lead systems. These characteristics help extend battery life, which for the current generation of 3D eyewear approaches 1,000 hr of continuous operation with two 3-V batteries. Improving power efficiency is crucial because miniaturizing the product further reduces the available space for batteries, most likely as the need for performance escalates.

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